W90N745CD/W90N745CDG
Host Controller Command Status Register
RESET
REGISTER
ADDRESS
R/W
DESCRIPTION
VALUE
HcCommandStatus 0xFFF0_5008
R/W Host Controller Command Status Register 0x0000_0000
31
30
29
28
20
27
Reserved
26
25
24
23
15
7
22
14
6
21
13
5
19
18
10
17
9
16
8
Reserved
12
11
Reserved
4
3
2
1
0
Reserved
OCR
BLF
CLF
HCR
BITS
DESCRIPTION
[31:18]
Reserved
SOC
Reserved
ScheduleOverrunCount
[17:16]
[15:4]
[3]
This field is increment every time the SchedulingOverrun bit in
HcInterruptStatus is set. The count wraps from ‘11’ to ‘00.’
Reserved
OCR
Reserved. Read/Write 0's
OwnershipChangeRequest
When set by software, this bit sets the OwnershipChange field in
HcInterruptStatus. The bit is cleared by software.
BulkListFilled
Set to indicate there is an active ED on the Bulk List. The bit may be
set by either software or the Host Controller and cleared by the Host
Controller each time it begins processing the head of the Bulk List.
[2]
BLF
ControlListFilled
Set to indicate there is an active ED on the Control List. It may be set
by either software or the Host Controller and cleared by the Host
Controller each time it begins processing the head of the Control List.
[1]
[0]
CLF
HostControllerReset
HCR
This bit is set to initiate the software reset. This bit is cleared by the
Host Controller, upon completed of the reset operation.
Publication Release Date: September 22, 2006
- 173 -
Revision A2
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