W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTION
FrameNumberOverflowEnable
[5]
[4]
[3]
FNOE
UREE
RDTE
0: Ignore
1: Enable interrupt generation due to Frame Number Overflow.
UnrecoverableErrorEnable
This event is not implemented. All writes to this bit are ignored.
ResumeDetectedEnable
0: Ignore
1: Enable interrupt generation due to Resume Detected.
StartOfFrameEnable
[2]
[1]
[0]
SOFE
WDHE
SCHOE
0: Ignore
1: Enable interrupt generation due to Start of Frame.
WritebackDoneHeadEnable
0: Ignore
1: Enable interrupt generation due to Write-back Done Head.
SchedulingOverrunEnable
0: Ignore
1: Enable interrupt generation due to Scheduling Overrun.
Host Controller Interrupt Disable Register
Writing a ‘1’ to a bit in this register clears the corresponding bit, while writing a ‘0’ to a bit leaves the bit
unchanged.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
HcInterruptEnable
0xFFF0_5014
R/W Host Controller Interrupt Disable Register 0x0000_0000
31
MIE
23
30
OCE
22
29
28
27
19
26
25
24
Reserved
21
13
20
12
18
10
2
17
9
16
8
Reserved
15
14
11
Reserved
7
6
5
4
3
1
0
Reserved
RHSCE
FNOE
UREE
RDTE
SOFE
WDHE
SCHOE
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