W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTION
WritebackDoneHead
[1]
[0]
WDH
Set after the Host Controller has written HcDoneHead to
HccaDoneHead.
SchedulingOverrun
SCHO
Set when the List Processor determines a Schedule Overrun has
occurred.
Host Controller Interrupt Enable Register
Writing a ‘1’ to a bit in this register sets the corresponding bit, while writing a ‘0’ leaves the bit
unchanged.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
HcInterruptEnable
0xFFF0_5010
R/W Host Controller Interrupt Enable Register 0x0000_0000
31
30
29
28
27
19
26
Reserved
25
24
MIE
23
OCE
22
21
13
20
12
18
17
9
16
8
Reserved
11
Reserved
15
14
10
7
6
5
4
3
2
1
0
Reserved
RHCE
FNOE
UREE
RDTE
SOFE
WDHE
SCHOE
BITS
DESCRIPTION
MasterInterruptEnable
[31]
MIE
This bit is a global interrupt enable. A write of ‘1’ allows interrupts to
be enabled via the specific enable bits listed above.
OwnershipChangeEnable
[30]
[29:7]
[6]
OCE
0: Ignore
1: Enable interrupt generation due to Ownership Change.
Reserved. Read/Write 0's
Reserved
RHSCE
RootHubStatusChangeEnable
0: Ignore
1: Enable interrupt generation due to Root Hub Status Change.
Publication Release Date: September 22, 2006
- 175 -
Revision A2
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