W90N745CD/W90N745CDG
Host Controller Interrupt Status Register
All bits are set by hardware and cleared by software.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
HcInterruptStatus 0xFFF0_500C
R/W Host Controller Interrupt Status Register 0x0000_0000
31
30
29
28
27
19
26
Reserved
25
24
Reserved
23
OCH
22
21
13
20
12
18
17
9
16
8
Reserved
11
Reserved
15
14
10
7
6
5
4
3
2
1
0
Reserved
RHSC
FNO
URE
RDT
SOF
WDH
SCO
BITS
DESCRIPTION
[31]
Reserved
OCH
Reserved
OwnershipChange
[30]
[29:7]
[6]
This bit is set when the OwnershipChangeRequest bit of
HcCommandStatus is set.
Reserved
RootHubStatusChange
RHSC
FNO
This bit is set when the content of HcRhStatus or the content of any
HcRhPortStatus register has changed.
FrameNumberOverflow
[5]
[4]
Set when bit 15 of FrameNumber changes value.
UnrecoverableError
URE
This event is not implemented and is hard-coded to ‘0.’ Writes are
ignored.
ResumeDetected
[3]
[2]
RDT
SOF
Set when Host Controller detects resume signaling on a downstream
port.
StartOfFrame
Set when the Frame Management block signals a ‘Start of Frame’
event.
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