W90N745CD/W90N745CDG
Interrupt Processing
Interrupts are the communication method for HC-initiated communication with the Host Controller
Driver. There are several events that may trigger an interrupt from the Host Controller. Each specific
event sets a specific bit in the HcInterruptStatus register.
Host Controller Bus Master
The Host Controller Bus Master is the central block in the data path. The Host Controller Bus Master
coordinates all access to the AHB Interface. There are two sources of bus mastering within Host
Controller: the List Processor and the Data Buffer Engine.
Data Buffer
The Data Buffer serves as the data interface between the Bus Master and the SIE. It is a combination
of a 64-byte latched based bi-directional asynchronous FIFO and a single Dword AHB Holding
Register.
6.7.1.3. USB Interface
The USB interface includes the integrated Root Hub with two external ports, Port 1 and Port 2 as well
as the Serial Interface Engine (SIE) and USB clock generator. The interface combines responsibility
for executing bus transactions requested by the HC as well as the hub and port management
specified by USB.
6.7.2 USB Host Controller Registers Map
REGISTER
OpenHCI Registers
HcRevision
ADDRESS R/W
DESCRIPTION
RESET VALUE
0xFFF0_5000
0xFFF0_5004
0xFFF0_5008
0xFFF0_500C
0xFFF0_5010
0xFFF0_5014
R
Host Controller Revision Register
0x0000_0010
0x0000_0000
HcControl
R/W Host Controller Control Register
HcCommandStatus
HcInterruptStatus
HcInterruptEnbale
HcInterruptDisbale
R/W Host Controller Command Status Register 0x0000_0000
R/W Host Controller Interrupt Status Register
R/W Host Controller Interrupt Enable Register
0x0000_0000
0x0000_0000
R/W Host Controller Interrupt Disable Register 0x0000_0000
Host Controller Communication Area
HcHCCA
0xFFF0_5018
R/W
0x0000_0000
Register
Host Controller Period Current ED
Register
HcPeriodCurrentED
HcControlHeadED
HcControlCurrentED
0xFFF0_501C
0xFFF0_5020
0xFFF0_5024
R/W
0x0000_0000
R/W Host Controller Control Head ED Register 0x0000_0000
Host Controller Control Current ED
Register
R/W Host Controller Bulk Head ED Register
R/W
0x0000_0000
HcBulkHeadEd
0xFFF0_5028
0xFFF0_502C
0x0000_0000
HcBulkCurrentED
R/W Host Controller Bulk Current ED Register 0x0000_0000
Publication Release Date: September 22, 2006
- 169 -
Revision A2
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