W90N745CD/W90N745CDG
Channel 0/1 Current Destination Register (GDMA_CDST0, GDMA_CDST1)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
Channel 0 Current Destination Address
Register
GDMA_CDST0 0xFFF0_4014
GDMA_CDST1 0xFFF0_4034
R
0x0000_0000
Channel 1 Current Destination Address
Register
R
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
CURRENT_DST_ADDR [31:24]
20 19
CURRENT_DST_ADDR [23:16]
12 11
CURRENT_DST_ADDR [15:8]
27
26
18
10
2
25
24
16
8
17
9
4
3
1
0
CURRENT_DST_ADDR [7:0]
BITS
DESCRIPTIONS
The 32-bit Current Destination Address indicates the
destination address where the GDMA transfer is just
occurring. During a block transfer, the GDMA determines
the successive destination addresses by adding to or
subtracting from the destination base address. Depending
on the settings you make to the control register, the current
destination address will remain the same or will be
incremented or decremented.
[31:0]
CURRENT_DST_ADDR
Channel 0/1 Current Transfer Count Register (GDMA_CTCNT0,
GDMA_CTCNT1)
The Current transfer count register indicates the number of transfer being performed.
RESET
VALUE
REGISTER
ADDRESS
R/W
DESCRIPTION
GDMA_CTCNT0
GDMA_CTCNT1
Channel 0 Current Transfer Count Register
Channel 1 Current Transfer Count Register
0xFFF0_4018
0xFFF0_4038
R
R
0x0000_0000
0x0000_0000
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