W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTIONS
The Enable Receive Descriptor Unavailable Interrupt controls the
RDU interrupt generation. If RDU of MISTA register is set, and both
EnRDU and EnTXINTR are enabled, the EMC generates the Rx
interrupt to CPU. If EnRDU or EnTXINTR is disabled, no Rx interrupt is
generated to CPU even the RDU of MISTA register is set.
[10]
EnRDU
EnDEN
EnDFO
EnMMP
EnRP
1’b0: RDU of MISTA register is masked from Rx interrupt generation.
1’b1: RDU of MISTA register can participate in Rx interrupt generation.
The Enable DMA Early Notification Interrupt controls the DENI
interrupt generation. If DENI of MISTA register is set, and both EnDEN
and EnTXINTR are enabled, the EMC generates the Rx interrupt to
CPU. If EnDEN or EnTXINTR is disabled, no Rx interrupt is generated
to CPU even the DENI of MISTA register is set.
[9]
1’b0: DENI of MISTA register is masked from Rx interrupt generation.
1’b1: DENI of MISTA register can participate in Rx interrupt generation.
The Enable Maximum Frame Length Interrupt controls the DFOI
interrupt generation. If DFOI of MISTA register is set, and both EnDFO
and EnTXINTR are enabled, the EMC generates the Rx interrupt to
CPU. If EnDFO or EnTXINTR is disabled, no Rx interrupt is generated
to CPU even the DFOI of MISTA register is set.
[8]
1’b0: DFOI of MISTA register is masked from Rx interrupt generation.
1’b1: DFOI of MISTA register can participate in Rx interrupt generation.
The Enable More Missed Packet Interrupt controls the MMP interrupt
generation. If MMP of MISTA register is set, and both EnMMP and
EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If
EnMMP or EnTXINTR is disabled, no Rx interrupt is generated to CPU
even the MMP of MISTA register is set.
[7]
1’b0: MMP of MISTA register is masked from Rx interrupt generation.
1’b1: MMP of MISTA register can participate in Rx interrupt generation.
The Enable Runt Packet Interrupt controls the RP interrupt
generation. If RP of MISTA register is set, and both EnRP and
EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If
EnRP or EnTXINTR is disabled, no Rx interrupt is generated to CPU
even the RP of MISTA register is set.
[6]
1’b0: RP of MISTA register is masked from Rx interrupt generation.
1’b1: RP of MISTA register can participate in Rx interrupt generation.
Publication Release Date: September 22, 2006
- 133 -
Revision A2
WINBOND [ WINBOND ]
