W90N745CD/W90N745CDG
MAC Interrupt Enable Register (MIEN)
The MIEN controls the enable of EMC interrupt status to generate interrupt. Two interrupts, RXINTR
for frame reception and TXINTR for frame transmission, are generated from EMC to CPU.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
MIEN
0xFFF0_30AC R/W MAC Interrupt Enable Register
0x0000_0000
31
30
29
28
Reserved
20
27
19
26
18
25
17
24
EnTxBErr
16
23
EnTDU
15
22
EnLC
14
21
EnTXABT
13
EnNCS
12
EnEXDEF EnTXCP EnTXEMP EnTXINTR
11
10
9
8
EnDFO
0
Reserved EnCFR
Reserved
EnRxBErr EnRDU
EnDEN
1
7
6
5
4
3
2
EnMMP
EnRP
EnALIE
EnRXGD
EnPTLE
EnRXOV
EnCRCE
EnRXINTR
BITS
DESCRIPTIONS
[31:25]
Reserved
EnTxBErr
-
The Enable Transmit Bus Error Interrupt controls the TxBErr
interrupt generation. If TxBErr of MISTA register is set, and both
EnTxBErr and EnTXINTR are enabled, the EMC generates the Tx
interrupt to CPU. If EnTxBErr or EnTXINTR is disabled, no Tx interrupt
is generated to CPU even the TxBErr of MISTA register is set.
[24]
1’b0: TxBErr of MISTA register is masked from Tx interrupt generation.
1’b1: TxBErr of MISTA register can participate in Tx interrupt
generation.
The Enable Transmit Descriptor Unavailable Interrupt controls the
TDU interrupt generation. If TDU of MISTA register is set, and both
EnTDU and EnTXINTR are enabled, the EMC generates the Tx
interrupt to CPU. If EnTDU or EnTXINTR is disabled, no Tx interrupt is
generated to CPU even the TDU of MISTA register is set.
[23]
EnTDU
1’b0: TDU of MISTA register is masked from Tx interrupt generation.
1’b1: TDU of MISTA register can participate in Tx interrupt generation.
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