W90N745CD/W90N745CDG
Continued
BITS
DESCRIPTIONS
The Enable Late Collision Interrupt controls the LC interrupt
generation. If LC of MISTA register is set, and both EnLC and
EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If
EnLC or EnTXINTR is disabled, no Tx interrupt is generated to CPU
even the LC of MISTA register is set.
[22]
[21]
[20]
[19]
EnLC
1’b0: LC of MISTA register is masked from Tx interrupt generation.
1’b1: LC of MISTA register can participate in Tx interrupt generation.
The Enable Transmit Abort Interrupt controls the TXABT interrupt
generation. If TXABT of MISTA register is set, and both EnTXABT and
EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If
EnTXABT or EnTXINTR is disabled, no Tx interrupt is generated to
CPU even the TXABT of MISTA register is set.
EnTXABT
1’b0: TXABT of MISTA register is masked from Tx interrupt generation.
1’b1: TXABT of MISTA register can participate in Tx interrupt
generation.
The Enable No Carrier Sense Interrupt controls the NCS interrupt
generation. If NCS of MISTA register is set, and both EnNCS and
EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If
EnNCS or EnTXINTR is disabled, no Tx interrupt is generated to CPU
even the NCS of MISTA register is set.
EnNCS
1’b0: NCS of MISTA register is masked from Tx interrupt generation.
1’b1: NCS of MISTA register can participate in Tx interrupt generation.
The Enable Defer Exceed Interrupt controls the EXDEF interrupt
generation. If EXDEF of MISTA register is set, and both EnEXDEF and
EnTXINTR are enabled, the EMC generates the Tx interrupt to CPU. If
EnEXDEF or EnTXINTR is disabled, no Tx interrupt is generated to
CPU even the EXDEF of MISTA register is set.
EnEXDEF
1’b0: EXDEF of MISTA register is masked from Tx interrupt generation.
1’b1: EXDEF of MISTA register can participate in Tx interrupt
generation.
The Enable Transmit Completion Interrupt controls the TXCP
interrupt generation. If TXCP of MISTA register is set, and both
EnTXCP and EnTXINTR are enabled, the EMC generates the Tx
interrupt to CPU. If EnTXCP or EnTXINTR is disabled, no Tx interrupt
is generated to CPU even the TXCP of MISTA register is set.
[18]
EnTXCP
1’b0: TXCP of MISTA register is masked from Tx interrupt generation.
1’b1: TXCP of MISTA register can participate in Tx interrupt
generation.
Publication Release Date: September 22, 2006
- 131 -
Revision A2
WINBOND [ WINBOND ]
