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W90N745CDG 参数 Datasheet PDF下载

W90N745CDG图片预览
型号: W90N745CDG
PDF下载: 下载PDF文件 查看货源
内容描述: 16位/ 32位ARM微控制器 [16/32-bit ARM microcontroller]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 422 页 / 2455 K
品牌: WINBOND [ WINBOND ]
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W90N745CD/W90N745CDG  
Continued.  
BITS  
DESCRIPTIONS  
The Late Collision Interrupt high indicates the collision occurred in the  
outside of 64 bytes collision window. This means after the 64 bytes of a  
frame has transmitted out to the network, the collision still occurred.  
The late collision check will only be done while EMC is operating on  
half-duplex mode.  
[22]  
LC  
If the LC is high and EnLC of MIEN register is enabled, the TxINTR will  
be high. Write 1 to this bit clears the LC status.  
1’b0: No collision occurred in the outside of 64 bytes collision window.  
1’b1: Collision occurred in the outside of 64 bytes collision window.  
The Transmit Abort Interrupt high indicates the packet incurred 16  
consecutive collisions during transmission, and then the transmission  
process for this packet is aborted. The transmission abort is only  
available while EMC is operating on half-duplex mode.  
If the TXABT is high and EnTXABT of MIEN register is enabled, the  
TxINTR will be high. Write 1 to this bit clears the TXABT status.  
[21]  
TXABT  
1’b0: Packet doesn’t incur 16 consecutive collisions during  
transmission.  
1’b1: Packet incurred 16 consecutive collisions during transmission.  
The No Carrier Sense Interrupt high indicates the MII I/F signal CRS  
doesn’t active at the start of or during the packet transmission. The  
NCS is only available while EMC is operating on half-duplex mode.  
If the NCS is high and EnNCS of MIEN register is enabled, the TxINTR  
will be high. Write 1 to this bit clears the NCS status.  
[20]  
NCS  
1’b0: CRS signal actives correctly.  
1’b1: CRS signal doesn’t active at the start of or during the packet  
transmission.  
The Defer Exceed Interrupt high indicates the frame waiting for  
transmission has deferred over 0.32768ms on 100Mbps mode, or  
3.2768ms on 10Mbps mode. The deferral exceed check will only be  
done while bit NDEF of MCMDR is disabled, and EMC is operating on  
half-duplex mode.  
If the EXDEF is high and EnEXDEF of MIEN register is enabled, the  
TxINTR will be high. Write 1 to this bit clears the EXDEF status.  
[19]  
EXDEF  
1’b0: Frame waiting for transmission has not deferred over 0.32768ms  
(100Mbps) or 3.2768ms (10Mbps).  
1’b1: Frame waiting for transmission has deferred over 0.32768ms  
(100Mbps) or 3.2768ms (10Mbps).  
Publication Release Date: September 22, 2006  
- 137 -  
Revision A2  
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