W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTIONS
The Enable CRC Error Interrupt controls the CRCE interrupt
generation. If CRCE of MISTA register is set, and both EnCRCE and
EnTXINTR are enabled, the EMC generates the Rx interrupt to CPU. If
EnCRCE or EnTXINTR is disabled, no Rx interrupt is generated to
CPU even the CRCE of MISTA register is set.
[1]
EnCRCE
1’b0: CRCE of MISTA register is masked from Rx interrupt generation.
1’b1: CRCE of MISTA register can participate in Rx interrupt
generation.
The Enable Receive Interrupt controls the Rx interrupt generation.
If EnRXINTR is enabled and RXINTR of MISTA register is high, EMC
generates the Rx interrupt to CPU. If EnRXINTR is disabled, no Rx
interrupt is generated to CPU even the status bits 1~14 of MISTA are
set and the corresponding bits of MIEN are enabled. In other words, if
S/W wants to receive Rx interrupt from EMC, this bit must be enabled.
And, if S/W doesn’t want to receive any Rx interrupt from EMC,
disables this bit.
[0]
EnRXINTR
1’b0: RXINTR of MISTA register is masked and Rx interrupt generation
is disabled.
1’b1: RXINTR of MISTA register is unmasked and Rx interrupt
generation is enabled.
Publication Release Date: September 22, 2006
- 135 -
Revision A2
WINBOND [ WINBOND ]
