W90N745CD/W90N745CDG
FIFO Threshold Control Register (FFTCR)
The FFTCR defines the high and low threshold of internal FIFOs, including TxFIFO and RxFIFO. The
threshold of internal FIFOs is related to EMC request generation and when the frame transmission
starts. The FFTCR also defines the burst length of AHB bus cycle for system memory access.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
FIFO Threshold Control Register
FFTCR
0xFFF0_309C
R/W
0x0000_0101
31
23
30
22
14
6
29
21
13
28
27
19
11
3
26
18
10
2
25
24
16
Reserved
20
12
4
17
Reserved
9
Reserved
BLength
15
8
TxTHD
0
Reserved
5
7
1
Reserved
RxTHD
BITS
DESCRIPTIONS
[31:22]
Reserved
Blength
-
The DMA Burst Length defines the burst length of AHB bus cycle
while EMC accesses system memory.
2’b00: 4 words
2’b01: 8 words
2’b10: 16 words
2’b11: 16 words
[21:20]
[19:10]
Reserved
-
- 126 -
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