W90N745CD/W90N745CDG
Transmit Start Demand Register (TSDR)
If the Tx descriptor is not available for use of TxDMA after the TXON of MCMDR register is enabled,
the FSM (Finite State Machine) of TxDMA enters the Halt state and the frame transmission is halted.
After the S/W has prepared the new Tx descriptor for frame transmission, it must issue a write
command to TSDR register to make TxDMA leave Halt state and contiguous frame transmission. The
TSDR is a write only register and read from this register is undefined. The write to TSDR register has
took effect only while TxDMA stayed at Halt state.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
TSDR
0xFFF0_30A0
W
Transmit Start Demand Register
Undefined
BITS
DESCRIPTIONS
[31:0]
Reserved
-
Receive Start Demand Register (RSDR)
If the Rx descriptor is not available for use of RxDMA after the RXON of MCMDR register is enabled,
the FSM (Finite State Machine) of RxDMA enters the Halt state and the frame reception is halted.
After the S/W has prepared the new Rx descriptor for frame reception, it must issue a write command
to RSDR register to make RxDMA leave Halt state and contiguous frame reception. The RSDR is a
write only register and read from this register is undefined. The write to RSDR register has took effect
only while RxDMA stayed at Halt state.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
RSDR
0xFFF0_30A4
W
Receive Start Demand Register
Undefined
BITS
DESCRIPTIONS
[31:0]
Reserved
--
- 128 -
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