W83759A
Pin Description, continued
SYMBOL
SP1
PIN
TYPE
I/O
DESCRIPTION
67
When SYSRST is active, this pin is an input that latches on the
rising edge of SYSRST .
/IDEA0
-PD
SP1: VL-Bus speed select. A high input configures the W83759A
to run at from 33 MHz to 50 MHz; a low input configures the
W83759A to run at under 33 MHz.
IDEA0: IDE drive address bit 0. Drive address bit 0 is output to
the IDE connector for register selection in the drive.
IDD[15:0]
I/O
72- 87
When SYSRST is active, these pins function as inputs and latch
on the rising edge of SYSRST .
-PU
As power-on setting pins, IDD[15:8] are latched to the POSS3
register and IDD[7:0] are latched to the POSS2 register.
As the drive data bus, bits 15 through 0 are the 16-bit bidirectional
data bus that connects to the IDE drive.
IDD[7:0] define the lowest data byte. The IDD bus is normally in a
pull-high state and is driven with valid data by the W83759A only
during IDE or VGA ( VGAOEH = 0 or
VGAOEL = 0) write cycles.
ISA-Bus Interface
SA[1:0]
SD[7:0]
47, 46
58-51
I
ISA address bits 1 and 0.
Used to select the hard disk I/O registers.
I/O
These signals provide data bus bits 0 through 7 for the CPU and
IDE I/O devices. SD0 is the least significant bit and SD7 is the
most significant bit.
48
49
50
I
I
I
XIOR
XIOR instructs the hard disk I/O device to drive its data onto the
SD data bus.
XIOW
AEN
XIOW instructs the hard disk I/O device to read the data on the
SD data bus.
When this line is active (high), the DMA controller has control of
the address bus. A low is the address enable.
Publication Release Date: May 1995
- 9 -
Revision A1
WINBOND [ WINBOND ]
