W83759A
Pin Description, continued
SYMBOL
PIN
TYPE
DESCRIPTION
94
I
Ready return.
RDYRTN
An active low signal that indicates the end of the current host
CPU transfer.
Usually RDYRTN is tied directly to the RDY signal of the host
CPU.
HA[9:2]
10-3
I
Host address bits 9 through 2 from the host address bus.
HD[31:0]
I/O
Host data.
11- 14
19- 39
42- 45
This is the 32-bit bidirectional data bus that connects to the host
CPU. HD[7:0] define the lowest data byte, while D[31:24] define
the most significant byte by the BE 2:0 signals. The HD bus is
normally in a high-impedance state and is driven by the
W83759A only during data register (1F0h or 170h) read cycles
and VGA ( VGAOEH = 0 or VGAOEL = 0) read cycles.
Drive Interface
PRDYEN
/IDE0CS0
61
I/O
When SYSRST is active, this is an input that latches on the
rising edge of SYSRST .
-PU
PRDYEN: A high input enables the IORDY flow control function of
the primary channel (IDE0) and a low input disables the IDE0's
flow control function.
IDE0CS0 : When SYSRST is inactive, this pin is an active low
output used to select the command block registers in the IDE0
drive (1F0h- 1F7h).
SRDYEN
/IDE0CS1
62
I/O
When SYSRST is active, this is an input that latches on the
rising edge of SYSRST .
-PU
SRDYEN: A high input enables the IORDY flow control function of
the secondary channel (IDE1) and a low disables the IDE1's flow
control function.
IDE0CS1: When SYSRST is inactive, this pin is an active low
output used to select the alternate status register of the control
block registers in the IDE0 drive (3F6).
- 6 -
WINBOND [ WINBOND ]
