W83759A
Pin Description, continued
SYMBOL
PIN
TYPE
I/O
DESCRIPTION
ENIDE
63
When SYSRST is active, this is an input that latches on the rising
edge of SYSRST .
-PU
/IDE1CS0
ENIDE: In W83759 mode (ADV = low), this power-on-setting pin
controls if the chip enable or disable. In W83759A mode (ADV =
high), this pin controls if the IDE0 channel enable or disable. A high
input enables and a low input disables the IDE0 channel.
IDE1CS0 : When SYSRST is inactive, this pin is an active low
output and is used to select the command block registers in the
IDE1 drive (170h- 177h).
TEST
64
I/O
When SYSRST is active, this is an input that latches on the rising
edge of SYSRST .
-PU
/IDE1CS1
TEST: In W83759 mode, this power-on-setting pin controls whether
both dual channels are enabled or only the primary channel is
enabled. A high input enables IDE0 and IDE1 simultaneously and a
low input enables IDE0 only. In W83759A mode, this pin controls
whether the IDE1 channel enable or disable controls the IDE0
channel as ENIDE.
IDE1CS1: When SYSRST is inactive, this pin is an active low
output used to select the alternate status register of the control
block registers in the IDE1 drive (376).
70
I/O
EMD1
When SYSRST is active, this is an input that latches on the rising
edge of SYSRST .
-PU
/IDEIOR
EMD1: This power-on-setting pin combines with EMD0 to set the
initial enhanced timing mode of hard disk access cycles when the
enhanced mode is selected via the POSS3 configuration register.
IDEIOR : Drive I/O read. An active low output that enables data to
be read from the drive. The duration and repetition rate of IDEIOR
cycles are determined by the type of IDE drive, as specified by
MD1 and MD0, in W83759 mode or by EMD1 and EMD0 in
W83759A enhanced mode.
Publication Release Date: May 1995
- 7 -
Revision A1
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