WED3DL644V
White Electronic Designs
CLOCK ENABLE (CKE) TRUTH TABLE
CKE
Command
Current State
Action
Notes
Previous Current
CE# RAS# CAS# WE# BA0-1 A10-11
Cycle
H
L
Cycle
X
X
H
L
L
L
L
X
X
H
L
L
H
L
L
L
L
H
L
L
L
L
X
X
X
H
H
H
L
X
X
X
X
H
X
H
L
L
L
X
H
L
L
L
X
X
X
H
H
L
X
X
X
X
X
L
X
X
H
L
X
X
X
X
X
X
L
X
X
X
H
L
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID
Exit Self Refresh with Device Deselect
Exit Self Refresh with No Operation
ILLEGAL
1
2
2
2
2
2
H
H
H
H
H
L
L
L
L
L
Self Refresh
ILLEGAL
ILLEGAL
L
Maintain Self Refresh
INVALID
Power Down Mode exit, all banks idle
ILLEGAL
H
L
L
X
1
2
2
2
H
H
X
H
H
H
H
H
L
L
L
L
H
X
Power Down
All Banks Idle
H
H
H
H
H
H
H
H
H
H
H
L
Maintain Power Down Mode
X
X
H
L
Refer to the Idle State section of the
Current State Truth Table
3
X
X
X
CBR Refresh
Mode Register Set
L
OP Code
4
3
4
4
X
X
H
L
L
X
Refer to the Idle State section of the
Current State Truth Table
Entry Self Refresh
X
OP Code
Mode Register Set
Power Down
X
X
X
X
Refer to the Operations in the Current
H
H
X
X
X
X
X
State Truth Table
Any State other
than listed above
H
L
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain Clock Suspend
5
Notes:
1.
2.
For the given Current State CKE must be low in the previous cycle.
When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (tCKS) must be satisfied before
any command other than Exit is issued.
3.
4.
5.
The address inputs (A11-A0) depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information.
The Power Down Mode, Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state.
Must be a legal command as defined in the Current State Truth Table.
August 2005
Rev. 6
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
