W3H64M72E-XSBX
White Electronic Designs
ADVANCED*
WRITE COMMAND
DQS edge is WT tDQSS. Subsequent DQS positive rising
edges are timed, relative to the associated clock edge, as
tDQSS. tDQSS is specified with a relatively wide range
(25 percent of one clock cycle).All of the WRIꢀE diagrams
show the nominal case, and where the two extreme cases
ꢀhe WRIꢀE command is used to initiate a burst write
access to an active row. ꢀhe value on the BA2–BA0 inputs
selects the bank, and the address provided on inputsA0–9
selects the starting column location. ꢀhe value on input
A10 determines whether or not auto precharge is used.
If auto precharge is selected, the row being accessed
will be precharged at the end of the WRIꢀE burst; if auto
precharge is not selected, the row will remain open for
subsequent accesses.
t
(tDQSS [MIN] and DQSS [MAX]) might not be intuitive,
they have also been included. Upon completion of a burst,
assuming no other commands have been initiated, the
DQ will remain High-Z and any additional input data will
be ignored.
Input data appearing on the DQ is written to the memory
array subject to the DM input logic level appearing
coincident with the data. If a given DM signal is registered
TOW, the corresponding data will be written to memory; if
the DM signal is registered HIGH, the corresponding data
inputs will be ignored, and a WRIꢀE will not be executed
to that byte/column location.
Data for any WRIꢀE burst may be concatenated with a
subsequent WRIꢀE command to provide continuous flow
of input data. ꢀhe first data element from the new burst is
applied after the last element of a completed burst. ꢀhe
new WRIꢀE command should be issued x cycles after the
first WRIꢀE command, where x equals BT/2.
DDR2 SDRAM supports concurrent auto precharge
options, as shown in ꢀable 4.
WRITE OPERATION
WRIꢀE bursts are initiated with a WRIꢀE command, as
shown in Figure 12. DDR2 SDRAM uses WT equal to RT
minus one clock cycle [WT = RT - 1CK = AT + (CT - 1CK)].
ꢀhe starting column and bank addresses are provided
with the WRIꢀE command, and auto precharge is either
enabled or disabled for that access. If auto precharge is
enabled, the row being accessed is precharged at the
completion of the burst.
DDR2 SDRAM does not allow interrupting or truncating
any WRIꢀE burst using BT = 4 operation. Once the BT
= 4 WRIꢀE command is registered, it must be allowed
to complete the entire WRIꢀE burst cycle. However,
a WRIꢀE (with auto precharge disabled) using BT = 8
operation might be interrupted and truncated ONTY by
another WRIꢀE burst as long as the interruption occurs
on a 4-bit boundary, due to the 4n prefetch architecture of
DDR2 SDRAM. WRIꢀE burst BT = 8 operations may not
to be interrupted or truncated with any command except
another WRIꢀE command.
During WRIꢀE bursts, the first valid data-in element will
be registered on the first rising edge of DQS following the
WRIꢀE command, and subsequent data elements will be
registered on successive edges of DQS. ꢀhe TOW state
on DQS between the WRIꢀE command and the first rising
edge is known as the write preamble; the TOW state on
DQS following the last data-in element is known as the
write postamble.
Data for any WRIꢀE burst may be followed by a
subsequent READ command. ꢀhe number of clock cycles
required to meet tWꢀR is either 2 or tWꢀR/tCK, whichever
is greater. Data for any WRIꢀE burst may be followed by a
subsequent PRECHARGE command. tWꢀ starts at the end
of the data burst, regardless of the data mask condition.
ꢀhe time between the WRIꢀE command and the first rising
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
19
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
