W3H64M72E-XSBX
White Electronic Designs
ADVANCED*
DESELECT
ꢀhe DESETECꢀ function (CS# HIGH) prevents new
commands from being executed by the DDR2 SDRAM.
ꢀhe DDR2 SDRAM is effectively deselected. Operations
already in progress are not affected.
entered. ꢀhe same procedure is used to convert other
specification limits from time units to clock cycles. For
t
example, a RCD (MIN) specification of 20ns with a 266
MHz clock (tCK = 3.75ns) results in 5.3 clocks, rounded
up to 6.
NO OPERATION (NOP)
A subsequent ACꢀIVE command to a different row in the
same bank can only be issued after the previous active
row has been closed (precharged). ꢀhe minimum time
interval between successive ACꢀIVE commands to the
same bank is defined by tRC
ꢀhe NO OPERAꢀION (NOP) command is used to instruct
the selected DDR2 SDRAM to perform a NOP (CS# is
TOW; RAS#, CAS#, and WE are HIGH). ꢀhis prevents
unwanted commands from being registered during idle
or wait states. Operations already in progress are not
affected.
A subsequent ACꢀIVE command to another bank can be
issued while the first bank is being accessed, which results
in a reduction of total row-access overhead. ꢀhe minimum
time interval between successive ACꢀIVE commands to
different banks is defined by tRRD
LOAD MODE (LM)
ꢀhe mode registers are loaded via inputs BA2–BA0, and
A12–A0. BA2–BA0 determine which mode register will
be programmed. See “Mode Register (MR)”. ꢀhe TM
command can only be issued when all banks are idle, and
a subsequent execute able command cannot be issued
until tMRD is met.
FIGURE 10 – ACTIVE COMMAND
BANK/ROW ACTIVATION
ACTIVE COMMAND
CK#
CK
ꢀhe ACꢀIVE command is used to open (or activate) a
row in a particular bank for a subsequent access. ꢀhe
value on the BA2–BA0 inputs selects the bank, and the
address provided on inputs A12–A0 selects the row.
ꢀhis row remains active (or open) for accesses until
a PRECHARGE command is issued to that bank. A
PRECHARGE command must be issued before opening
a different row in the same bank.
CKE
CS#
RAS#
CAS#
WE#
ACTIVE OPERATION
Before any READ or WRIꢀE commands can be issued to
a bank within the DDR2 SDRAM, a row in that bank must
be opened (activated), even when additive latency is used.
ꢀhis is accomplished via the ACꢀIVE command, which
selects both the bank and the row to be activated.
Row
ADDRESS
BANK ADDRESS
Bank
After a row is opened with an ACꢀIVE command, a READ
or WRIꢀE command may be issued to that row, subject to
the tRCD specification. tRCD (MIN) should be divided by
the clock period and rounded up to the next whole number
to determine the earliest clock edge after the ACꢀIVE
command on which a READ or WRIꢀE command can be
DON’ꢀ CARE
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
17
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
