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W3H64M72E-ESC 参数 Datasheet PDF下载

W3H64M72E-ESC图片预览
型号: W3H64M72E-ESC
PDF下载: 下载PDF文件 查看货源
内容描述: 64M X 72 DDR2 SDRAM 208 PBGA多芯片封装 [64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package]
分类和应用: 存储内存集成电路动态存储器双倍数据速率
文件页数/大小: 30 页 / 942 K
品牌: WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
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W3H64M72E-XSBX  
White Electronic Designs  
ADVANCED*  
FIGURE 9 – EXTENDED MODE REGISTER 3 (EMR3) DEFINITION  
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A 6 A5 A4 A3 A2 A1 A0  
Address Bus  
Exten ded Mo de  
Register (Ex)  
16 15 14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0
01  
01 01 01 01 01 01 01 01 01 01 01  
01 01  
EMR3  
Mode Register Definition  
M1 6 M15 M14  
Mode register (MR)  
0
1
0
1
0
0
0
0
0
0
1
1
Extended mode register (EMR)  
Extended mode register (EMR2)  
Extended mode register (EMR3)  
Note: 1. E13 (A13)-E0 (A0) are reserved for future use and must be programmed to  
"0." A13 is not used in this device.  
EXTENDED MODE REGISTER 2  
not alter the contents of the memory array, provided it is  
performed correctly.  
ꢀhe extended mode register 2 (EMR2) controls functions  
beyond those controlled by the mode register. Currently  
all bits in EMR2 are reserved, as shown in Figure 8. ꢀhe  
EMR2 is programmed via the TM command and will  
retain the stored information until it is programmed again  
or the device loses power. Reprogramming the EMR will  
not alter the contents of the memory array, provided it is  
performed correctly.  
EMR3 must be loaded when all banks are idle and no  
bursts are in progress, and the controller must wait the  
t
specified time MRD before initiating any subsequent  
operation. Violating either of these requirements could  
result in unspecified operation.  
Bit E7 (A7) must be programmed as"1" to provide a faster  
refresh rate on devices if the ꢀCASE exceeds 85°C  
COMMAND TRUTH TABLES  
ꢀhe following tables provide a quick reference of DDR2  
SDRAM available commands, including CKE power-down  
modes, and bank-to-bank commands.  
EMR2 must be loaded when all banks are idle and no  
bursts are in progress, and the controller must wait the  
t
specified time MRD before initiating any subsequent  
operation. Violating either of these requirements could  
result in unspecified operation.  
EXTENDED MODE REGISTER 3  
ꢀhe extended mode register 3 (EMR3) controls functions  
beyond those controlled by the mode register. Currently,  
all bits in EMR3 are reserved, as shown in Figure 9.  
ꢀhe EMR3 is programmed via the TM command and will  
retain the stored information until it is programmed again  
or the device loses power. Reprogramming the EMR will  
White Electronic Designs Corp. reserves the right to change products or specifications without notice.  
March 2006  
Rev. 1  
15  
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com