SCA3000 Series
4.2.1.2 I2C read mode
The read mode operates as described in Philips I2C specification. I2C read operation returns the
content of the register which address is defined in I2C_RD_SEL register. So when performing the
I2C read operation, the register address to be read has to be written into I2C_RD_SEL register
before actual read operation. Read operation starts from register address that has been written
earlier in I2C_RD_SEL register. Read data is acknowledged by I2C master. Automatic read
address change depends on the selected start address (see cases 3 and 4 in Figure 10).
-
If address is some of registers between X_LSB Æ Z_MSB the register address is automatically
cycled as follows:
... ÆY_MSB Æ Y_LSB Æ X_MSB Æ X_LSB Æ Z_MSB Æ Z_LSB Æ Y_MSB Æ Y_LSB Æ ...
If the start address is any other register, the read address is NOT automatically incremented or
decremented (the data transfer continues from the same address.) This enables the burst read
from output ring buffer (register BUF_DATA).
-
4.2.1.3 Decremented register read
Decremented reading is possible only for registers X_LSB ... Z_MSB. Refer to decremented read
with SPI interface section 4.1.3.2.
4.2.2 Examples of I2C communication
Examples of I2C communication are presented below in Figure 10.
Read/write select bit
(0=write, 1=read)
CASE 1: I2C 8 bit write
register addr
8 bits, MSB first
register data
device addr 2nd byte
AAAAAAAA
device addr 1st byte
11110AA
S
S
S
0
SA
E
SA
SA
8 bits, MSB first
SA
CASE 2: I2C 16 bit write (any number of bytes can be written, length is determined by end condition generated by master)
register data, addr + 0
8 bits, MSB first
device addr 1st byte
11110AA
register data, addr - 1
8 bits, MSB first
device addr 2nd byte
AAAAAAAA
register addr
8 bits, MSB first
SA
SA
SA
SA
SA
E
0
CASE 3: I2C 8 bit read, read address for SCA3000 series register should be written to I2C_RD_SEL register
register data, addr
8 bits, MSB first
device addr 2nd byte
AAAAAAAA
device addr 1st byte
11110AA
device addr 1st byte
11110AA
E
MA
0
SA
SARS
1 SA
CASE 4: I2C 16 bit read (any number of bytes can be read, length is determined by end condition generated by master).
Automatic register address changing depends on selected start address in I2C_RD_SEL (noted by addr and addr_x on the figure).
device addr 2nd byte
AAAAAAAA
device addr 1st byte
11110AA
device addr 1st byte
11110AA
register data, addr
register data, addr_x
SA
MA
8 bits, MSB first
S
E
MA
SA
1 SA
8 bits, MSB first
0
RS
S
= Start condition
RS = Repeated start condition
= End condition
E
SA = Slave Acknowledgement
MA = Master Acknowledgement
AA = Device address, 10 bits
Figure 10. I2C frame format.
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