SCA3000 Series
TLS1
TCH
TCL
TLS2
TLH
CSB
SCK
THOL
TSET
MOSI
MISO
MSB in
DATA in
LSB in
TVAL1
TVAL2
TLZ
MSB out
DATA out
LSB out
Figure 11. Timing diagram for SPI communication.
Table 21. AC characteristics of SPI communication.
Parameter
Conditions
Symbol
Min
Typ
Max
Unit
Terminal CSB, SCK
Time from CSB (10%)
to SCK (90%)1
Time from SCK (10%)
to CSB (90%)1
TLS1
TLS2
Tper/2
Tper/2
ns
ns
1
2
Terminal SCK
3
4
5
SCK low time
Load
TCL
0.80*
Tper/2
Tper/2
Tper/2
ns
ns
capacitance at
MISO < 35 pF
Load
capacitance at
MISO < 35 pF
SCK high time
TCH
0.80*
Tper/2
SCK Frequency
fsck =
1/Tper
Product
specific
MHz
Terminal MOSI, SCK
6
Time from changing
TSET
Tper/4
Tper/4
ns
ns
MOSI (10%, 90%) to
SCK (90%)1. Data
setup time
Time from SCK (90%)
to changing MOSI
(10%, 90%)1. Data
hold time
7
THOL
Terminal MISO, CSB
8
Time from CSB (10%)
to stable MISO (10%,
90%)
Time from CSB (90%)
to high impedance
state of MISO1.
Load
TVAL1
Tper/4
Tper/4
ns
ns
capacitance at
MISO < 35 pF
Load
capacitance at
MISO < 35 pF
9
TLZ
Terminal MISO, SCK
10 Time from SCK (10%)
to stable MISO (10%,
90%)1.
Load
capacitance at
MISO < 35 pF
TVAL2
1.3· Tper/4
ns
ns
Terminal MOSI, CSB
11 Time between SPI
cycles, CSB at high
level (90%)
TLH
4 · Tper
Tper is SCK period
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