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SCA3000-E05-1 参数 Datasheet PDF下载

SCA3000-E05-1图片预览
型号: SCA3000-E05-1
PDF下载: 下载PDF文件 查看货源
内容描述: [Analog Circuit]
分类和应用:
文件页数/大小: 45 页 / 1038 K
品牌: VTI [ VTI TECHNOLOGIES ]
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SCA3000 Series  
4
Serial Interfaces  
Communication between the SCA3000 sensor and master controller is based on serial data  
transfer and a dedicated interrupt line (INT-pin). Two different serial interfaces are available for the  
SCA3000 sensor: SPI and I2C (Phillips specification V2.1). However, only one per product is  
enabled by pre-programming in the factory. The SCA3000 acts as a slave on both the SPI and I2C  
bus.  
4.1 SPI Interface  
SPI bus is a full duplex synchronous 4-wire serial interface. It consists of one master device and  
one or more slave devices. The master is defined as a micro controller providing the SPI clock, and  
the slave as any integrated circuit receiving the SPI clock from the master. The SCA3000 sensor  
always operates as a slave device in master-slave operation mode. A typical SPI connection is  
presented in Figure 5.  
MASTER  
MICROCONTROLLER  
SLAVE  
SI  
DATA OUT (MOSI)  
DATA IN (MISO)  
SO  
SERIAL CLOCK (SCK)  
SCK  
SS0  
SS1  
CS  
SI  
SS2  
SS3  
SO  
SCK  
CS  
SI  
SO  
SCK  
CS  
SI  
SO  
SCK  
CS  
Figure 5. Typical SPI connection.  
The data transfer uses the following 4-wire interface:  
MOSI  
MISO  
SCK  
master out slave in  
master in slave out  
serial clock  
µC SCA3000  
SCA3000 → µC  
µC SCA3000  
µC SCA3000  
CSB  
chip select (low active)  
4.1.1 SPI frame format  
SCA3000 SPI frame format and transfer protocol is presented in Figure 6.  
Figure 6. SPI frame format.  
Each communication frame contains 16 bits. The first 8 bits in MOSI line contains info about the  
operation (read/write) and the register address being accessed. The first 6 bits define the 6 bit  
address for the selected operation, which is defined by bit 7 (‘0’ = read ‘1’ = write), which is  
VTI Technologies Oy  
www.vti.fi  
PRELIMINARY - Subject to changes  
Doc.Nr. 8257300A.06  
26/ 45  
Rev.A.06