SCA3000 Series
4.1.4.1 SCA3000-D03 in SPI bus with other slave devices
When using the SCA3000-D03 in SPI bus where other slave devices are connected to same bus,
the I2C communication can be disabled by using the following routine:
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Write 00h to register UNLOCK (addr. 1Eh)
Write 50h to register UNLOCK (addr. 1Eh)
Write A0h to register UNLOCK (addr. 1Eh)
Write 01h to register CRTL_SEL (addr. 18h)
Write 00h to register CTRL_DATA (addr. 22h)
See section 3.4 for register details.
4.1.4.2 SCA3000-L01 in SPI bus with other slave devices
When using the SCA3000-L01 in SPI bus where other slave devices are connected to same bus,
the I2C communication can be disabled by using the following routine:
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•
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Write 00h to register UNLOCK (addr. 1Eh)
Write 50h to register UNLOCK (addr. 1Eh)
Write A0h to register UNLOCK (addr. 1Eh)
Write 01h to register CRTL_SEL (addr. 18h)
Write 40h to register CTRL_DATA (addr. 22h)
See section 3.4 for register details.
4.2 I2C Interface
I2C is a 2-wire serial interface. It consists of one master device and one or more slave devices. The
master is defined as a micro controller providing the serial clock (SCL), and the slave as any
integrated circuit receiving the SCL clock from the master. The SCA3000 sensor always operates
as a slave device in master-slave operation mode. When using an SPI interface, a hardware
addressing is used (slaves have dedicated CSB signals), the I2C interface uses a software based
addressing (slave devices have dedicated bit patterns as addresses).
The SCA3000 is compatible to the Philips I2C specification V2.1. Main used features of the I2C
interface are:
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10-bit addressing, SCA3000 I2C device address is 0x1F1
Supports standard mode and fast mode
Start / Restart / Stop
Slave transceiver mode
Designed for low power consumption
In addition to the Philips specification, the SCA3000 I2C interface supports multiple write and read
mode.
4.2.1 I2C frame format
4.2.1.1 I2C write mode
In I2C write mode, the first 8 bits after device address define the SCA3000 internal register address
to be written. If multiple data words are transferred by the master, the register address is
decreased automatically by one (see cases 1 and 2 in Figure 10).
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