SCA8X0/21X0/3100 Series
5
6
SCK Frequency
fsck =
1/Tper
8
MHz
ns
Terminal MOSI, SCK
Time from changing
MOSI (10%, 90%) to
SCK (90%)1. Data setup
time
TSET
Tper/4
Tper/4
7
Time from SCK (90%) to
changing MOSI (10%,
THOL
ns
90%)1. Data hold time
Terminal MISO, CSB
8
9
Time from CSB (10%) to Load capacitance at
stable MISO (10%, 90%) MISO < 50 pF
Time from CSB (90%) to Load capacitance at
TVAL1
TLZ
Tper/4
Tper/4
ns
ns
high impedance state of
MISO1.
MISO < 50 pF
Terminal MISO, SCK
10 Time from SCK (10%) to Load capacitance at
TVAL2
1.3 x
Tper/4
ns
ns
stable MISO (10%,
90%)1.
MISO < 50 pF
Terminal CSB
11 Time between SPI
cycles, CSB at high level
(90%)
TLH
Tper
TLS1
TCH
TCL
TLS2
TLH
CSB
SCK
THOL
TSET
MOSI
MISO
MSB in
DATA in
LSB in
TVAL1
TVAL2
TLZ
MSB out
DATA out
LSB out
Figure 6: Timing diagram of SPI communication
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