Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
VIS
Figure 13.3 Read and Write Cycle (Burst Length = 4, CAS Latency = 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK3
CKE
CS
RAS
CAS
WE
DSF
BS
RAx
A9
A0 ~ A8
CAx
CAy
RAx
CAz
DQM
DQ
Hi-Z
DAy1
DAy0
Write
DAy3
Az3
Ax0
Az0 Az1
Ax1 Ax2 Ax3
Read
The Read Data
Read
Activate
Command
The Write Data
Command
is Masked with a
Two Clock
Latency
Command
Command
Bank A
Bank A
is Masked with a
Zero Clock
Latency
Bank A
Bank A
Document:
Rev.1
Page27