Preliminary
VG37648041AT
256M:x4, x8, x16
VIS
CMOS Synchronous Dynamic RAM
Data from any READ burst may be truncated with a BURST TERMINATE command, as shown in Figure 11. The
BURST TERMINATE latency is equal to the read (CAS) latency, i.e. the BURST TERMINATE command should be
issued x cycles after the READ command, where x equals the number of desired data element pairs (pairs are
required by the 2n prefetch architecture).
Data from any READ burst must be completed or truncated before a subsequent WRITE command can be
issued. If truncation is necessary, the BURST TERMINATE command must be used, as shown in Figure 12. The
tDDS MIN case is shown; the tDDS MAX case has a longer bus idle time (tDDS MIN and tDDS MAX are defined in
the section on WRITEs).
A READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that
AUTO PRECHARGE was not activated). The PRECHARGE command should be issued x cycles after the READ
command, where x equals the number of desired data element paires (pairs are required by the 2n prefetch architec-
ture). This is shown if Figure 13 for READ latencies of 2.2.5 and 3. Following the PRECHARGE command, a subse-
t
quent command to the same bank cannot be issued until RP is met. Note that part of the row precharge time is
hidden during the access of the last data elements.
In the case of a READ being executed to completion. a PRECHARGE command issued at the optimum time
(asdescribed above) provides the same operation that would result from the same READ burst with AUTO PRE-
CHARGE enabled. The disadvantage of the precharge command is that it requires that the command and address
buses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command is
that it can be used to truncate bursts.
Document : 1G5-0157
Rev.1
Page31
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
