Preliminary
VG37648041AT
256M:x4, x8, x16
VIS
CMOS Synchronous Dynamic RAM
CLK#
CLK
COMMAND
ADDRESS
READ
READ
NOP
READ
READ
Bank,
Col g
Bank,
Col n
Bank,
Col x
Bank,
Col b
CL=1.5
DQS
DQ
DO
b
DO
b’
DO
x’
DO
n’
DO
x
DO
n
CLK#
CLK
COMMAND
ADDRESS
READ
READ
NOP
READ
NOP
READ
Bank,
Col g
Bank,
Col x
Bank,
Col b
Bank,
Col n
CL=3
DQS
DQ
DO
b
DO
x’
DO
n’
DO
x
DO
n
DONT’ CARE
UNDEFINED
DO n, etc.= Data Out from column n, etc.
n’, etc.=odd or even complement of n, etc. (i.e. column address LSB inverted)
Burst Length=2,4 or 8 in cases shown
Reads are to active rows in any banks
Figure 10b
RANDOM READ ACCESSES - OPTIONAL CAS LATENCIES
Document : 1G5-0157
Rev.1
Page30
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
