Preliminary
VG37648041AT
256M:x4, x8, x16
VIS
CMOS Synchronous Dynamic RAM
CLK#
CLK
COMMAND
ADDRESS
READ
NOP
NOP
BST
NOP
NOP
Bank a,
Col n
CL=2
DQS
DQ
DO
n
CLK#
CLK
COMMAND
ADDRESS
READ
NOP
NOP
BST
NOP
NOP
Bank a,
Col n
CL=2.5
DQS
DQ
DO
n
DONT’ CARE
UNDEFINED
DO n=Data Out from column n
Cases shown are bursts of 8 terminated after 4 data elements
3 subsequent elements of Data Out appear in the programmed order following DO n
Figure 11a
TERMINATING A READ BURST - REQUIRED CAS LATENCIES
Document : 1G5-0157
Rev.1
Page32