Preliminary
VG37648041AT
256M:x4, x8, x16
VIS
CMOS Synchronous Dynamic RAM
CLK#
CLK
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
READ
Bank,
Col b
Bank,
Col n
CL=1.5
DQS
DQ
DO
b
DO
n
CLK#
CLK
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
NOP
READ
Bank,
Col n
Bank,
Col b
CL=3
DQS
DQ
DO
b
DO
n
DONT’ CARE
UNDEFINED
DO n(or b)=Data Out from column n (or column b)
Burst Length=4
3 Subsequent elements of Data Out appear in the programmed order following DO n(and following DO b)
Figure 9b
NON-CONSECUTIVE READ BURSTS-OPTIONAL CAS LATENCIES
Document : 1G5-0157
Rev.1
Page28