Preliminary
VG37648041AT
256M:x4, x8, x16
VIS
CMOS Synchronous Dynamic RAM
CLK#
CLK
COMMAND
ADDRESS
READ
NOP
NOP
READ
NOP
NOP
Bank,
Col n
Bank,
Col b
CL=2
DQS
DQ
DO
b
DO
n
CLK#
CLK
COMMAND
ADDRESS
READ
NOP
NOP
READ
NOP
NOP
Bank,
Col b
Bank,
Col n
CL=2.5
DQS
DQ
DO
b
DO
n
DONT’ CARE
UNDEFINED
Do n(or b)= Data Out from column n (or column b)
Burst Length= 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first)
3 subsequent elements of Data Out appear in the programmed order following DO n
3 (or 7) subsequent elements of Data Out appear in the programmed order following DO b
Figure 8a
CONSECUTIVE READ BURSTS - REQUIRED CAS LATENCIES
Document : 1G5-0157
Rev.1
Page25
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
