VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
VIS
AC Parameters for Write Timing (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CL
t
CK2
t
CH
t
Begin Auto Precharge
Bank A
Begin Auto Precharge
CMS
t
(Bank D)
Bank B
t
CKS
CKH
t
CMH
CS
RAS
CAS
WE
BS
A10
t
AH
t
AS
ADD
DQM
DQ
t
RCD
t
t
t
DAL
DS
RRD
t
t
t
RC
DPL
RP
t
DH
QAa0
QAa1
QBa1 QBa2 QBa3 QAb0 QAb1 QAb2
QAa2 QAa3 QBa0
QAb3
Activate
Command
Bank A
Write without
Activate
Command
Bank A
Activate
Command
Bank B
Write with Activate
Auto Precharge Command
Write with
Auto Precharge
Command
Precharge
Command
Bank A
Activate
Command
Bank B
(Bank D)
Auto Precharge
Command
Bank A
Command
Bank B
Bank A
(Bank D)
Bank A
(Bank D)
Document:1G5-0189
Rev.1
Page29
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
