VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
VIS
Power on Sequence and Auto Refresh (CBR)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
High level
is required
RSC
Minimum of 8 Refresh Cycles are required
CS
RAS
CAS
WE
A11(BS)
A10
Address Key
A0~A9
DQM
DQ
High Level is Necessary
t
t
RP
RC
Mode
Register
Set Command
2nd Auto
Refresh
Command
Command
Inputs
must
be stable
for 200us
Precharge
Command
All Banks
1st Auto
Refresh
Command
Document:1G5-0189
Rev.1
Page33