VG3617161ET
1,048,576 x 16 - Bit
CMOS Synchronous Dynamic RAM
VIS
AC Parameters for Write Timing (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CLK
t
CL
t
t
CK3
CH
t
Begin Auto Precharge
Bank A
Begin Auto Precharge
Bank B (Bank D)
CMS
t
t
CKE
CS
CKS
CKH
t
CMH
RAS
CAS
WE
BS
A10
ADD
t
AH
t
AS
DQM
DQ
t
RCD
t
t
t
DAL
RRD
DS
t
t
t
RC
DPL
RP
t
DH
QAa0
QAa1 QAa2
QAb3
QAa3 QBa0 QBa1 QBa2 QBa3
QAb0 QAb1 QAb2
Precharge
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank A
Write without
Auto Precharge
Command
Write with
Activate
Command
Bank B
(Bank D)
Write with
Auto Precharge
Command
Bank B
Activate
Command
Bank A
Auto Precharge
Command
Bank A
Bank A
(Bank D)
Document:1G5-0189
Rev.1
Page30
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
