VG26(V)(S)17400FJ
4,194,304 x 4 - Bit
CMOS Dynamic RAM
VIS
DC Characteristics ; 3.3 - Volt Version (cont.)
(Ta = 0 to 70°C, VCC = + 3.3V(+10%,-5%), VSS= 0V)
VG26 (V) (S) 17400E
-5 -6
Min Max Min Max
Parameter
Symbol
Test Conditions
Unit Notes
Input leakage
current
Output leakage
current
ILI
-5
5
-5
5
mA
mA
V
0V £ Vin £ VCC + 0.3V
ILO
-5
5
-5
5
0V £ Vout £ VCC + 0.3V
Dout = Disable
lOH = -2mA
Output high
voltage
Output low
voltage
VOH
VOL
2.4
-
-
2.4
-
-
lOL = + 2mA
0.4
0.4
V
Notes :
1. lCC is specified as an average current. It depends on output loading condition and cycle rate when
the device is selected. lCC max is specified at the output open condition.
2. Address can be changed once or less while RAS = VIL.
3. For lCC4, address can be changed once or less within one Fast page mode cycle time.
Document :
Rev.
Page9
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
