128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
[ Write Interrupted by Precharge ]
Burstwriteoperationcanbeinterrupted byprechargeofthesamebank.Writerecoverytime(tWR)isrequiredfromthelastdata
to PRE command. During write recovery, data inputs must be masked by DQM.
Write Interrupted by Precharge (BL=4)
CLK
Command
A0-9,11
A10
ACT
Xa
0
Write
Ya
0
PRE
ACT
Xa
0
tRP
0
BA0-1
DQM
00
00
00
00
tWR
DQ
Da 0
Da 1
[Write Interrupted by Burst Terminate]
Burst terminate command can terminate burst write operation.In this case, the write recovery time is not required and the
bankremainsactive. WRITEtoTBSTintervalisminimum1CLK.
Write Interrupted by Terminate (BL=4)
CLK
Command
A0-9,11
A10
ACT
Xa
0
Write
Ya
TBST
Write
Yb
0
0
BA0-1
DQ
00
00
00
Da 0
Da 1
Db0
Db1
Db2
Db3
JULY.2000
Rev.2.2
Page-24
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
