128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
[ Read Interrupted by Precharge ]
Burst read operation can be interrupted by precharge of the
same bank . READ to PRE interval is minimum 1 CLK. A PRE
command to output disable latency is equivalent to the /CAS
Latency. As a result, READ to PRE interval determines valid
data length to be output. The figure below shows examples of
BL=4.
Read Interrupted by Precharge (BL=4)
CLK
Command
DQ
PRE
READ
READ
READ
Q0
Q1
Q1
Q2
Command
DQ
PRE
CL=3
Q0
Command
DQ
PRE
Q0
Command
DQ
READ
READ
PRE
Q1
Q0
Q2
PRE
Q0
Command
DQ
CL=2
Q1
Command
DQ
READ PRE
Q0
JULY.2000
Rev.2.2
Page-21
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
