128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any bank. Random column access is allowed. WRITE to WRITE
interval is minimum 1 CLK.
Write Interrupted by Write (CL=3,BL=4)
CLK
Command
A0-9
Write Write
Write
Yk
0
Write
Yl
Yi
0
Yj
0
A10
0
A11
BA0,1
DQ
00
00
10
00
Dai0 Daj0 Daj1 Dbk0 Dbk1 Dbk2 Dal0 Dal1 Dal2 Dal3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank. Random column access is allowed. WRITE
to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is "don't care".
Write Interrupted by Read (CL=3,BL=4)
CLK
Command
A0-9
Write READ
Write
READ
Yi
0
Yj
0
Yk
0
Yl
0
A10
A11
BA0,1
DQM
DQ
00
00
10
00
Dai0
Qaj0 Qaj1
Dbk0 Dbk1
Qal0
JULY.2000
Rev.2.2
Page-23
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
