VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
High Performance Serial
Backplane Transceiver
VSC870
Figure 5: Multicast Recast Functional Timing (Beginning of Multicast)
WCLK
TXIN[31:0]
HDR
2
D1 D2 D3
CRQ
3
D0
1
TXTYP[1:0]
ACK/RCLK
Min 9 word clocks
6 word clocks
REN
RTM/TCLK
RFM
Figure 6: Multicast Recast Functional Timing (At the End of Packet then Recast)
WCLK
D1-0
1
D3-0 D4-0
CRQ-N HDR-N D0-N D0-0
TXIN[31:0]
TXTYP[1:0]
ACK/RCLK
D2-0
1
3
2
REN
RTM/TCLK
RFM
NOTE: CRQ-N, HDR-N, D0-N: CRQ, header and first data word of the next packet;
these bytes are ignored by the transceiver during recast.
D0-0, D1-0, D2-0...:
Data words of the recasted packet.
2.3.7 Unicast Multi Queue Mode (MD[1:0] = 10)
Muti Queue mode assumes there are several unicast data queues on each port card such as virtual output queues
or priority queues, and allows the port card to make multiple connection requests at the same time. The switch chip
performs two levels of arbitration in two word clock cycles. The first level determines which of the requested outputs
are available and holds these outputs. The second level chooses one winner from the available outputs then releases
the rest. Because outputs can be blocked during the first level of arbitration, all Muti Queue CRQ commands are held
at the switch chip and continue to request outputs until one is granted. As in section 2.3.5, if an ACK is not received
before a header word is detected at the parallel interface, a repeated sequence of CRQs are sent to the switch chip
until an output is granted. This sequence depends on the value of CT[2:0]. The port number of the granted output
(P[3:0]) is returned to the port card following the ACK pulse on the ACK/RCLK output. The functional timing
diagram for this mode is shown in Figure 7.
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Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 22
G52190-0, Rev 4.1
01/05/01
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
