VSC8601 Datasheet
Contents
Figures
Figure 1.
Typical Application...................................................................................... 14
High-level Block Diagram ............................................................................ 16
RGMII to Cat5 Block Diagram ...................................................................... 17
RGMII MAC Interface.................................................................................. 18
Cat5 Media Interface .................................................................................. 19
Inline Powered Ethernet Switch Diagram....................................................... 22
ActiPHY State ............................................................................................ 24
SMI Read Frame ........................................................................................ 26
SMI Write Frame........................................................................................ 26
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10. MDINT Configured as an Open-Drain (Active-Low) Pin..................................... 27
Figure 11. MDINT Configured as an Open-Source (Active-High) Pin.................................. 27
Figure 12. Far-End Loopback ...................................................................................... 32
Figure 13. Near-End Loopback .................................................................................... 32
Figure 14. Connector Loopback................................................................................... 32
Figure 15. Test Access Port and Boundary-Scan Architecture........................................... 34
Figure 16. Register Space Diagram.............................................................................. 37
Figure 17. EEPROM Read and Write Register Flow.......................................................... 68
Figure 18. JTAG Interface Timing ................................................................................ 77
Figure 19. SMI Interface Timing.................................................................................. 78
Figure 20. Reset Timing............................................................................................. 79
Figure 21. RGMII Uncompensated Timing..................................................................... 81
Figure 22. RGMII Compensated Timing ........................................................................ 82
Figure 23. Pin Diagram .............................................................................................. 84
Figure 24. Package Drawing ....................................................................................... 94
Revision 4.1
September 2009
Page 6
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
