VSC8601 Datasheet
Contents
Contents
Revision History..........................................................................................9
1
2
Introduction.....................................................................................13
Product Overview.............................................................................14
2.1 Features ........................................................................................................... 14
2.2 Applications....................................................................................................... 15
2.3 Block Diagram ................................................................................................... 16
3
Functional Descriptions....................................................................17
3.1 Interface and Media............................................................................................ 17
3.2 MAC Interface.................................................................................................... 17
3.2.1
MAC Resistor Calibration.......................................................................... 17
3.2.2
RGMII MAC Interface Mode ...................................................................... 17
3.3 Cat5 Media Interface .......................................................................................... 18
3.4 Cat5 Auto-Negotiation ........................................................................................ 19
3.5 Manual MDI/MDI-X Setting .................................................................................. 20
3.6 Automatic Crossover and Polarity Detection ........................................................... 20
3.7 Link Speed Downshift ......................................................................................... 21
3.8 Transformerless Ethernet..................................................................................... 21
3.9 Ethernet Inline Powered Devices .......................................................................... 21
3.10 ActiPHY Power Management................................................................................. 23
3.10.1 Low-Power State .................................................................................... 24
3.10.2 Link Partner Wake-Up State ..................................................................... 25
3.10.3 Normal Operating State........................................................................... 25
3.11 Serial Management Interface ............................................................................... 25
3.11.1 SMI Frames ........................................................................................... 25
3.11.2 SMI Interrupts ....................................................................................... 27
3.12 LED Interface .................................................................................................... 28
3.12.1 Simple or Enhanced LED Method............................................................... 28
3.12.2 LED Modes............................................................................................. 28
3.12.3 LED Behavior ......................................................................................... 30
3.13 Testing Features................................................................................................. 30
3.13.1 Ethernet Packet Generator (EPG) .............................................................. 30
3.13.2 CRC Counters......................................................................................... 31
3.13.3 Far-end Loopback ................................................................................... 31
3.13.4 Near-End Loopback................................................................................. 32
3.13.5 Connector Loopback................................................................................ 32
3.13.6 VeriPHY Cable Diagnostics........................................................................ 33
3.13.7 IEEE 1149.1 JTAG Boundary Scan............................................................. 33
3.13.8 JTAG Instruction Codes............................................................................ 34
3.13.9 Boundary-Scan Register Cell Order............................................................ 36
4
Configuration...................................................................................37
4.1 Registers........................................................................................................... 37
4.1.1
Reserved Registers ................................................................................. 38
4.1.2
Reserved Bits......................................................................................... 38
4.2 IEEE Standard and Main Registers ........................................................................ 38
4.2.1
Mode Control ......................................................................................... 39
4.2.2
Mode Status........................................................................................... 40
Revision 4.1
September 2009
Page 3
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
