VSC8601 Datasheet
Contents
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
Consumption with 10BASE-T Link.............................................................. 72
Consumption with No Link and ActiPHY Enabled.......................................... 73
Consumption with No Link and ActiPHY Disabled ......................................... 73
Consumption in Power-Down Mode............................................................ 74
Consumption in Reset State ..................................................................... 75
5.3 AC Characteristics .............................................................................................. 75
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
Reference Clock Input ............................................................................. 76
Clock Output.......................................................................................... 76
JTAG Interface ....................................................................................... 77
SMI Interface......................................................................................... 77
Device Reset.......................................................................................... 78
RGMII Uncompensated............................................................................ 80
RGMII Compensated ............................................................................... 81
5.4 Operating Conditions .......................................................................................... 82
5.5 Stress Ratings ................................................................................................... 83
6
Pin Descriptions...............................................................................84
6.1 Pin Diagram ...................................................................................................... 84
6.2 Pins by Function................................................................................................. 85
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
Twisted Pair Interface.............................................................................. 85
RGMII MAC Interface .............................................................................. 86
Serial Management Interface (SMI)........................................................... 87
JTAG..................................................................................................... 88
Miscellaneous......................................................................................... 88
Power Supply......................................................................................... 89
Power Supply and Associated Function....................................................... 90
6.3 Pins by Name .................................................................................................... 91
6.4 Pins by Number ................................................................................................. 92
7
8
Package Information........................................................................93
7.1 Package Drawing................................................................................................ 93
7.2 Thermal Specifications........................................................................................ 95
7.3 Moisture Sensitivity ............................................................................................ 95
Design Considerations .....................................................................96
8.1 RX_CLK Can Reach as High as 55% Duty Cycle ...................................................... 96
8.2 First SMI Write Fails after Software Reset .............................................................. 96
8.3 Link-Up Issue In Forced 100BASE-TX Mode............................................................ 96
8.4 Default 10Base-T Settings Are Marginal and Cause MAU Test Failure.......................... 97
8.5 On-Chip Pull-up Resistor Violation......................................................................... 99
8.6 Setting the Internal RGMII Timing Compensation Value........................................... 99
8.7 10BASE-T Harmonics at 30 MHz and 50 MHz Marginally Violate Specification.............. 99
8.8 Voltage Overshoot When Using On-Chip Switching Regulator.................................. 100
8.9 Long Link-Up Times Caused by Noise on the Twisted Pair Interface ......................... 100
8.10 High VDD33 and Low VDDIOMAC Supply............................................................. 101
9
Ordering Information.....................................................................102
Revision 4.1
September 2009
Page 5
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
