VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8140
2.48832Gb/s 16:1 SONET/SDH
Transceiver with Integrated Clock Generator
Figure 7: Traditional DC Termination of Low-Speed LVPECL RXOUT[15:0] Outputs
VSC8140
Z
o
R1 =50Ω
V
CC
-2V
The RXOUT[15:0] output drivers can also be appropriately AC-coupled by a number of methods, how-
ever, DC-coupling is preferred since there is no guarantee of transition density for individual bits in the 16-bit
word. Figure 8 illustrates an AC-coupling method for the occasion when the downstream device provides the
bias point for AC-coupling. Figure 9 illustrates an AC-coupling method for the occasion when the bias point
needs to be generated externally. The resistor values in Figure 9 were selected to generate a bias point of 1.98V,
the mid-point for LVPECL V
OH
and V
OL
as specified for the VSC8140. Resistor values should be selected to
generate the necessary bias point for the downstream device.
Figure 8: AC Termination of Low-Speed LVPECL RXOUT[15:0] Outputs
VSC8140
Z
o
100nF
R1 = 50Ω
V
CC
-2V
downstream
bias point
generated
internally
G52251-0, Rev. 4.0
9/6/00
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 5
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
