VITESSE
SEMICONDUCTOR CORPORATION
2.48832Gb/s 16:1 SONET/SDH
Transceiver with Integrated Clock Generator
Figure 9: AC Termination of Low-Speed LVPECL RXOUT[15:0] Outputs
Data Sheet
VSC8140
VSC8140
V
CC
R1 = 125Ω
Z
o
V
CC
R3 =83Ω
downstream
100nF
R2 = 83Ω
V
EE
R4 = 125Ω
bias point
generated
externally
V
EE
Parity
Systems employing internal parity are supported by the VSC8140. On the transmit side, a parity check is
performed between the TXPARITYIN input and the 16 TXIN[15:0] bits.
PARMODE is used to select even or odd parity expected for these 17 bits. (TXIN[15:0] and TXPARI-
TYIN). PARMODE = “0” selects odd, PARMODE = “1” selects even. The PARERR output (parity error out-
put) is asserted active high when the parity of the 17 bits (TXIN[15:0] and TXPARITYIN) does not conform to
the expected parity designated by PARMODE. PARERR becomes available T
DV
after the rising edge of
TXCLK16I. PARERR is a NRZ pulse that is updated every 6.4 ns, i.e., the period of TXCLK16I. The timing
relationship of PARERR to TXCLK16I is shown in Figure 17. The PARERR pin may be left open if parity is
unused.
On the receive side, the parity output (RXPARITYOUT) is simply the XOR of all 16 outputs.
Loss of Signal
The VSC8140 has a TTL input LOS to force the part into a Loss of Signal (LOS) state. Most optics have a
TTL output usually called Signal Detect (SD), based on the optical power of the incoming light stream.
Depending on the optics manufacturer, this signal is either active high or low. To accommodate polarity differ-
ences, the internal Loss of Signal is generated when the POL and LOS inputs are of opposite states. Once active,
all zeroes “0” will be propagated downstream using the transmit clock until the optical signal is regained and
LOS and POL are in the same logic state.
Page 6
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52251-0, Rev. 4.0
9/6/00
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
