VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
VSC8113
Table 13: Clock Multiplier Unit Performance
Name
Description
Reference clock duty cycle
Min
Typ
Max
Units
RCd
RCj
40
60
13
12
9
%
ps
Reference clock jitter (RMS) @ 77.76 MHz ref (1)
Reference clock jitter (RMS) @ 51.84 MHz ref (1)
Reference clock jitter (RMS) @ 38.88 MHz ref (1)
Reference clock jitter (RMS) @ 19.44 MHz ref (1)
Reference clock frequency tolerance (2)
Output clock jitter (RMS) @ 77.76 MHz ref (3)
Output clock jitter (RMS) @ 51.84 MHz ref (3)
Output clock jitter (RMS) @ 38.88 MHz ref (3)
Output clock jitter (RMS) @ 19.44 MHz ref (3)
Output frequency
RCj
ps
RCj
ps
RCj
5
ps
RCf
-20
+20
8
ppm
ps
OCj
OCj
10
13
15
624
60
ps
OCj
ps
OCj
ps
OCfrange
OCd
620
40
MHz
%
Output clock duty cycle
(1)
These Reference Clock Jitter limits are required for the outputs to meet SONET system level jitter requirements
(< 10 mUIrms)
(2)
(3)
Needed to meet SONET output frequency stability requirements
Measured
Note: Jitter specification is defined utilizing a 12KHz - 5MHz LP-HP single pole filter.
AC Characteristics
Table 14: PECL and TTL Outputs
Parameters
Description
Min
Typ
Max Units
Conditions
10-90%
TR,TTL
TF,TTL
TR,PECL
TF,PECL
TTL Output Rise Time
TTL Output Fall Time
PECL Output Rise Time
PECL Output Fall Time
—
—
—
—
2
—
—
—
—
ns
ns
ps
ps
1.5
350
350
10-90%
20-80%
20-80%
Page 14
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52154-0, Rev 4.2
3/19/99
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
