VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
VSC8113
Data Latency
The VSC8113 contains several operating modes, each of which exercise different logic paths through the
part. Table 10 bounds the data latency through each path with an associated clock signal.
Table 10: Data Latency
Clock
Reference
Range of Clock
cycles
Circuit Mode
Description
Transmit
Receive
Data TXIN [7:0] to MSB at TXDATAOUT
MSB at RXDATAIN to data on RXOUT [7:0]
TXCLKOUT
RXCLKIN
4-13
25-35
Equipment
Loopback
Byte data TXIN [7:0] to byte data on RXOUT [7:0]
MSB at RXDATAIN to MSB at TXDATAOUT
TXCLKOUT
RXCLKIN
27-35
2-4
Facilities
Loopback
Clock Recovery Unit
Table 11: Reference Frequency for the CRU
CRUREFCLK
Frequency
[MHz]
Output
Frequency
[MHz]
CRUREFSEL
STS12
B2
B1
B0
1
1
0
1
X
X
X
77.76 ± 500ppm
77.76 ± 500ppm
622.08
155.52
0
X
X
X
Uses CMU’s Reference Clock (See Table 12 below)
Clock Multiplier Unit
Table 12: Reference Frequency Selection and Output Frequency Control
Reference
Frequency
[MHz]
Output
Frequency
[MHz]
STS12
B2
B1
B0
1
1
1
1
0
0
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
0
0
1
0
19.44
38.88
51.84
77.76
19.44
38.88
51.84
77.76
622.08
622.08
622.08
622.08
155.52
155.52
155.52
155.52
G52154-0, Rev 4.2
3/19/99
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 13
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