VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
VSC8113
Package Pin Description
Table 17: Pin Definitions
Signal
Pin
I/O
Level
Pin Description
Facility loopback, loops high speed receive data and clock
directly to transmit outputs.
FACLOOP
1
I
TTL
VDD
2
+3.3V
TTL
+3.3V Power Supply
CRUEQLP
RESET
3
I
I
I
I
I
I
Loops TXDATAOUT to the CRU replacing RXDATAIN+/-
Resets frame detection, dividers, controls; active high
Enable loop timing operation; active HIGH
Reference clock select, refer to table 12
Reference clock select, refer to table 12
Reference clock select, refer to table 12
+3.3V or +5V Power Supply for PECL I/Os
Transmit output, high speed differential data +
Transmit output, high speed differential data -
Ground
4
TTL
LOOPTIM0
B0
5
TTL
6
TTL
B1
7
TTL
B2
8
TTL
VDDP
9
+3.3/+5V
PECL
PECL
GND
TXDATAOUT+
TXDATAOUT-
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
O
O
TXCLKOUT+
TXCLKOUT-
VDDP
O
O
PECL
PECL
+3.3/+5V
Transmit high speed clock differential output+
Transmit high speed clock differential output-
+3.3V or +5V Power Supply for PECL I/Os
No connection
N/C
LOSDETEN_
VSS
I
TTL
GND
Enables internal LOS detection (active low).
Ground
RXCLKIN+
RXCLKIN-
VDDP
I
I
PECL
PECL
+3.3/+5V
TTL
Receive high speed differential clock input+
Receive high speed differential clock input-
+3.3V or +5V Power Supply for PECL I/Os
Out Of Frame; Frame detection initiated with high level
Disable on-chip clock recovery unit; active high
Receive high speed differential data input+
Receive high speed differential data input-
No connection
OOF
I
I
I
I
DSBLCRU
RXDATAIN+
RXDATAIN-
NC
TTL
PECL
PECL
NC
No connection
VDD
+3.3V
PECL
PECL
+3.3V Power Supply
REFCLKP+
REFCLKP-
I
I
PECL reference clock input+
PECL reference clock input-
G52154-0, Rev 4.2
3/19/99
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 17
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