VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
VSC8113
AC Timing Characteristics
Figure 8: Receive High Speed Data Input Timing Diagram
TRXCLK
RXCLKIN+
RXCLKIN-
TRXSU
TRXH
RXDATAIN+
RXDATAIN-
Table 2: Receive High Speed Data Input Timing Table (STS-12 Operation)
Parameter
Description
Min
Typ
Max
Units
TRXCLK
TRXSU
TRXH
Receive clock period
-
1.608
-
-
-
ns
ps
ps
Serial data setup time with respect to RXCLKIN
Serial data hold time with respect to RXCLKIN
250
250
-
-
Table 3: Receive High Speed Data Input Timing Table (STS-3 Operation)
Parameter
Description
Min
Typ
Max
Units
TRXCLK
TRXSU
TRXH
Receive clock period
-
6.43
-
-
-
ns
ns
ns
Serial data setup time with respect to RXCLKIN
Serial data hold time with respect to RXCLKIN
1.5
1.5
-
-
Figure 9: Transmit Data Input Timing Diagram
TPROP
TXLSCKOUT
TCLKIN
TXLSCKIN
TXIN [7:0]
TINH
TINSU
Page 10
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52154-0, Rev 4.2
3/19/99
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
