VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
VSC8113
Table 7: Receive Data Output Timing Table (STS-3 Operation)
Parameter
Description
Min
Typ
Max
Units
TRXCLKIN
TRXLSCKT
Receive clock period
-
-
6.43
-
-
ns
ns
Receive data output byte clock period
51.44
Time data on RXOUT [7:0] and FP is valid before and
after the rising edge of RXLSCKOUT
TRXVALID
TPW
22
-
-
-
-
ns
ns
Pulse width of frame detection pulse FP
51.44
Figure 11: Transmit High Speed Data Timing Diagram
TTXCLK
TXCLKOUT-
TXCLKOUT+
TSKEW
TSKEW
TXDATAOUT+
TXDATAOUT-
Table 8: Transmit High Speed Data Timing Table (STS-12 Operation)
Parameter
Description
Transmit clock period
Min
Typ
Max
Units
TTXCLK
-
1.608
-
ns
Skew between the falling edge of TXCLKOUT+ and
valid data on TXDATAOUT
TSKEW
-
-
250
ps
Table 9: Transmit High Speed Data Timing Table (STS-3 Operation)
Parameter
Description
Transmit clock period
Min
Typ
Max
Units
TTXCLK
-
6.43
-
ns
Skew between the falling edge of TXCLKOUT+ and
valid data on TXDATAOUT
TSKEW
-
-
250
ps
Page 12
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52154-0, Rev 4.2
3/19/99
VITESSE [ VITESSE SEMICONDUCTOR CORPORATION ]
