VSC8113
Data Sheet
Clock Multiplier Unit
Table 13. Reference Frequency Selection and Output Frequency Control
Reference Frequency
[MHz]
Output Frequency
[MHz]
STS12
B2
1
B1
1
B0
0
1
1
1
1
0
0
0
0
19.44
38.88
51.84
77.76
19.44
38.88
51.84
77.76
622.08
622.08
622.08
622.08
155.52
155.52
155.52
155.52
0
1
0
0
0
1
0
0
0
1
1
0
0
1
0
0
0
1
0
0
0
Table 14. Clock Multiplier Unit Performance
Name
Parameter
Min
Typ
Max
60
13
12
9
Unit
%
RC
RC
RC
RC
RC
RC
Reference clock duty cycle
40
D
J
(1)
Reference clock jitter (rms) at 77.76MHz reference
Reference clock jitter (rms) at 51.84MHz reference
Reference clock jitter (rms) at 38.88MHz reference
Reference clock jitter (rms) at 19.44MHz reference
ps
(1)
ps
J
(1)
(1)
ps
J
5
ps
J
(2)
Reference clock frequency tolerance
-20
+20
8
ppm
ps
F
(3)
OC
OC
OC
OC
Output clock jitter (rms) at 77.76MHz reference
J
J
J
J
(3)
Output clock jitter (rms) at 51.84MHz reference
10
13
15
624
60
60
ps
(3)
Output clock jitter (rms) at 38.88MHz reference
ps
(3)
Output clock jitter (rms) at 19.44MHz reference
ps
OCf
Output frequency
620
40
MHz
%
RANGE
OC
Output clock duty cycle
Reference clock duty cycle
VSC8113QB-03 Only:
D
RC
40
%
D
OD
85
mUIp-p
J
Output data jitter (peak-to-peak) at 77.76MHz reference
Jitter specification is defined utilizing a 12kHz to 5MHz LP-HP single pole filter.
1. These reference clock jitter limits are required for the outputs to meet SONET system level jitter requirements (<10 mUIrms).
2. Required to meet SONET output frequency stability requirements.
3. Measured.
13 of 22
G52154, Rev 4.5
6/28/02
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